Vhdl Code For 3 To 8 Decoder Using Dataflow Modelling

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  • For the VHDL code of the encoder using its truth tables and the dataflow architecture, we will use the when-else statements that we studied in the dataflow architecture post. The syntax is simple; we assign the output to a particular value and mention the condition followed by else statements.
  • 3 to 8 decoder VHDL source code. This page of VHDL source code covers 3 to 8 decoder vhdl code. Library IEEE; use IEEE.STDLOGIC1164.ALL.

3 to 8 Decoder: Verilog Code in Dataflow Modeling: module decoder3to8( input 2:0 a, output 7:0 d ); assign d. Decade counter Block diagram for Decade counter: Verilog code for Decade Counter/ MOD-10 Counter: (Behavioural model) module decade.

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This chapter explains the VHDL programming for Combinational Circuits.

VHDL Code for a Half-Adder

Waveforms

VHDL Code for a Full Adder

Waveforms

VHDL Code for a Half-Subtractor

Waveforms

VHDL Code for a Full Subtractor

Waveforms

Code

VHDL Code for a Multiplexer

Waveforms

VHDL Code for a Demultiplexer

Waveforms

VHDL Code for a 8 x 3 Encoder

Waveforms

VHDL Code for a 3 x 8 Decoder

Waveforms

VHDL Code – 4 bit Parallel adder

Waveforms

VHDL Code – 4 bit Parity Checker

Waveforms

VHDL Code – 4 bit Parity Generator

Waveforms

Objectives:

The objective of this experiment is to:
i. To revise the working of various logic gates
ii. To learn the VHDL coding
iii. To simulate for functional verification
iv. To implement on CPLD / FPGA

Symbols and Truth Table of Logic Gates:

Symbol NameSymbolTruth TableLogic Function
NOT Gate / Inverter
InputOutput
AY
0

1

1

0

Y = NOT A

Y = A’

OR Gate
InputOutput
ABY
000
011
101
111

Y = A OR B

Y = A + B

NOR Gate
InputOutput
ABY
001
010
100
110

Y = A NOR B

Y = (A + B)’

Y = NOT ( A OR B)

AND Gate
InputOutput
ABY
000
010
100
111

Y = A AND B

Y = A.B

NAND Gate

(Universal Gate)

InputOutput
ABY
001
010
100
110

Y = A NAND B

Y = (A.B)’

XOR Gate

(Universal Gate)

InputOutput
ABY
000
011
101
110

Y = A’B + AB’

Y = A XOR B

Y = A ⊕ B

VHDL Code to Design Logic Gates

[tabby title=”NOT Gate”]

NOT Gate Design

Function:

A NOT gate produces the complement of the input.

Modeling Style

Dataflow Modeling: This style uses the logic equation Y = A’

Behavioral Modeling: This style of modeling uses the algorithm for modeling. The behavior of a NOT gate states that the output is HIGH ‘1’ when input applied is LOW ‘0’ and vice versa.

VHDL Code for Synthesizing NOT Gate

Dataflow ArchitectureBehavioral Architecture
Library IEEE;

use IEEE.std_logic_1164.all;

entity NOT1 is

port (

A : in STD_LOGIC;

Y : out STD_LOGIC

);

end NOT1;

Architecture dataflow of NOT1 is

Begin

Y <= NOT A;

end dataflow;

Library IEEE;

use IEEE.std_logic_1164.all;

entity NOT1 is

port (

A : in STD_LOGIC;

Y : out STD_LOGIC

);

end not1;

Architecture behave of NOT1 is

begin

process (X)

begin

if (x=’0′) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of Inverter (NOT Gate)

[tabby title=”OR Gate”]

OR Gate

Function:

An OR gate is all pass gate. It produces a high output when any or all inputs are high.

Modeling Style

Designing>Dataflow Designing of OR GateBehavioral Modeling of OR GateLibrary IEEE;

use IEEE.std_logic_1164.all;

entity OR2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC

);

end OR2;

architecture behav1 of OR2 is

begin

Y <= A or B;

end behav1;

Library IEEE;

use IEEE.std_logic_1164.all;

entity OR2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC

);

end OR2;

architecture behav2 of OR2 is

begin

process (A, B)

Vhdl code for 3 to 8 decoder using dataflow modelling tutorial

begin

if (A = ‘0’ and B= ‘0’) then

Y <= ‘0’;

else

Y <= ‘1’;

end if;

end process;

end behav2;

Simulation of OR Gate

[tabby title=”AND Gate”]

AND Gate

Function:

An AND gate produces high output when all inputs are high

Modeling Style

Data flow/Concurrent Modeling: Make use of logic equation Y <= A.B

Sequential/Behavior Modeling : Make use of behavior algorithm i.e. AND gate produces a HIGH ‘1’ output when both A and B are high ‘1’, otherwise the output is LOW ‘0’

VHDL Code for Synthesizing AND Gate

Dataflow /Concurrent ModelingBehavior Modeling
Library IEEE;

use IEEE.std_logic_1164.all;

entity AND2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y: out STD_LOGIC

);

end AND2;

architecture dataflow of AND2 is

begin

Y <= A and B;

end dataflow;

Library IEEE;

use IEEE.std_logic_1164.all;

entity AND2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC

);

end AND2;

architecture behave of AND2 is

begin

process (A, B)

begin

if (A=’1′ and B=’1′) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of the AND Gate

[tabby title=”NOR Gate”]

Symbol

Function

A NOR gate is an OR followed by an INVERTER. It produces a high output when all inputs are low

Modeling Style

Dataflow /Concurrent Modeling: This style use the logic equations in design. For a NOR the logic eqn is Y = (A + B)’

Behavior / Sequential Modeling : This style of modeling for NOR Gate use the behavior /algorithm to describe the operation. For a NOR Gate the output is high when both A and B are LOW ‘0’ otherwise the output is HIGH ‘1’

VHDL Code for Synthesizing NOR Gate

Dataflow/Concurrent Style ModelingSequential / Behavioral Style Modeling
Library IEEE;

use IEEE.std_logic_1164.all;

entity nor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end nor2;

architecture dataflow of nor2 is

begin

Y <= A nor B;

end dataflow;

Library IEEE;

use IEEE.std_logic_1164.all;

entity nor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end nor2;

architecture behave of nor2 is

begin

process (A,B)

begin

If (A=’0′ and B=’0′) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of a NOR gate

[tabby title=”XOR Gate”]

XOR Gate

Symbol

Function

It produces a high when odd input are high, else produces a LOW output

Vhdl code for 3 to 8 decoder using dataflow modelling tutorial

Modeling Style

Dataflow/Concurrent Modeling : It makes use of the logic equation for modeling. The logic equation of an XOR Gate is : Y = (X’.Y +X .Y’)

Behavior / Sequential Modeling : This style of modeling makes use of the behavior or the algorithm of the operation. The XOR gate produces a HIGH ‘1’ output when one of its two input is high ‘1’ LOW ‘0’ otherwise.

VHDL Code for Synthesizing XOR Gate

Library IEEE;

use IEEE.std_logic_1164.all;

entity xor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end xor2;

architecture dataflow of xor2 is

begin

Y <= A xor B;

End dataflow;

Library IEEE;

use IEEE.std_logic_1164.all;

entity xor2 is

Port (

A: in STD_LOGIC;

B: in STD_LOGIC;

Y: out STD_LOGIC

);

end xor2;

architecture behav2 of xor2 is

begin

process (A, B)

begin

If (A/=B) then

Y <= ‘1’;

else

Y <= ‘0’;

end if;

end process;

end behave;

Simulation of XOR Gate

[tabby title=”NAND Gate”]

NAND Gate

Function: A NAND gate produces the complement of an AND gate. It produces a high output when any or all inputs are LOW ‘0’ else produces a LOW ‘0’

Modeling Style

Dataflow Style Modeling: It make use of the logic equation for modeling Y= (A.B)’

Vhdl code for 3 to 8 decoder using dataflow modelling data

Behavioral/Sequential Style Modeling:

Vhdl Code For 3 To 8 Decoder Using Dataflow Modelling Data

It makes use of the behavioral or algorithm for the synthesis. i.e. NAND gate produces a HOGH ‘1’ output when any or all inputs are low ‘0’, else it produces a the LOW output

VHDL Code for Synthesizing NAND Gate

Dataflow /Concurrent Style ModelingBehavioral / Sequential Style Modeling
Library IEEE;

use IEEE.std_logic_1164.all;

entity nand2 is

port(

A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC );

end nand2;

architecture behav1 of nand2 is

begin

Y <= A nand B;

end behav1;

Library IEEE;

use IEEE.std_logic_1164.all;

entity nand2 is

port(

A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC );

end nand2;

architecture behav2 of nand2 is

begin

Process (A, B)

Begin

If (A=’1′ and B=’1′) then

Y <= ‘0’;

else

Y <= ‘1’;

end if;

end process;

end behav2;

Simulation of NAND Gate

Vhdl Code For 3 To 8 Decoder Using Dataflow Modelling Tool

Vhdl code for 3 to 8 decoder using dataflow modelling tutorial

Vhdl Code For 3 To 8 Decoder Using Dataflow Modelling Tutorial

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